1. Field of the Invention
The present invention relates to a semiconductor memory device in which high-speed data transfer is carried out. The present invention also relates to an information apparatus using the semiconductor memory device and a method for determining an access period for the semiconductor memory device.
2. Description of the Related Art
A semiconductor memory device, such as an EEPROM (flash memory), requires a much longer time for the writing of data than that for an SRAM (Static Random Access Memory) and a DRAM (Dynamic Random Access Memory). Conventionally, in order to accelerate the write speed of such a semiconductor memory device, data is first accumulated in a buffer region comprising of another type of memory element, such as an SRAM and the like, which are incorporated into the semiconductor memory device, and the accumulated data is then transferred together to the semiconductor memory device (an EEPROM, etc.).
This method has the following drawbacks. For example, the buffer region is used only for a buffering function and there is a large limitation when the buffer region is used for other purposes. Typically, since data to be written into the buffer region is deployed in another memory in advance, the efficiency of memory use is low.
To solve these drawbacks, the present inventors previously disclosed a semiconductor memory device in Japanese Patent Application No. 2000-176182, in which a high-speed writable memory is incorporated without a buffer and further in which a data transfer section is provided between the high-speed writable memory and a non-volatile semiconductor memory element, such as an EEPROM and the like, thereby making it possible to further improve write speed and the efficiency of memory use.
With such a device, data can be transferred from a RAM for use in normal tasks to an EEPROM or the like, thereby making it unnecessary for write data to be deployed into a different region in advance, or for an EEPROM or the like to be separately controlled so as to write data to a buffer. Use of an incorporated high-speed writable memory in tasks of a system or the like essentially requires a simultaneous execution of an external memory operation and a data transfer operation. To this end, as the high-speed writable memory, a dual port memory was preferably used.
However, the dual port memory has drawbacks, such as a large increase in cell area, a degradation in characteristics of memory elements, and the like. Further, an increase in memory capacity disadvantageously leads to an increase in cost, an increase in an area occupied by elements, a decrease in performance, and the like.
The term xe2x80x9cexternal memory operationxe2x80x9d as used herein indicates that a memory is operated by a command issued from outside of the memory so that data is input to the memory issued from out side of the memory or is output outside of the memory.
The term xe2x80x9cexternallyxe2x80x9d in xe2x80x9cexternally readxe2x80x9d, xe2x80x9cexternally writtenxe2x80x9d, xe2x80x9cexternally instructedxe2x80x9d, and the like, as used herein indicates that such an operation is controlled by a command issued from outside so that data or instructions are transferred from or to outside of the memory.
FIG. 10 is a block diagram of an exemplary configuration of a conventional semiconductor memory device, showing major parts thereof. The semiconductor memory device carries out memory operations for a first conventional memory comprising of high write-speed memory elements and a second conventional memory comprising of low write-speed memory elements, and a data transfer operation which transfers data (the contents of the memory) between the memories. The semiconductor memory device will be described with reference to FIG. 10. In the data transfer operation, data is mainly transferred from the high write-speed memory to the low write-speed memory. Reverse data transfer is also useful since the load of an external control device or the like can be reduced. There is substantially no difference in the data transfer operation between both directions. Here, only data transfer from the high write-speed memory to the low write-speed memory will be described.
As shown in FIG. 10, a semiconductor memory device 490 comprises: a control bus 401 and a data bus 402 externally connected: a switching circuit 410 (MUX0) for transferring information to each section in accordance with external control instructions; a write state machine (WSM) 460 for controlling data transfer operations and the like; a memory 430 (MEM1), such as an SRAM and the like, comprising of high-speed writable memory elements; a switching circuit 420 (MUX1) for switching between control of the memory 430 instructed by the WSM 460 and control of the memory 430 externally instructed; a memory 450 (MEM2), such as a flash memory and the like, comprising of rewritable memory elements; and a switching circuit 440 (MUX2) for switching between control of the memory 450 instructed by the WSM 460 and control of the memory 450 externally instructed.
Control information is externally input to the semiconductor memory device 490 through the control bus 401 and the data bus 402 including address buses. When the control information is intended for the memory 430, the switching circuit 410 is used to transfer the control information via a control bus 411 and a data input/output bus 412 to the switching circuit 420. When the control information is intended for the memory 450, the control information is transferred via a control bus 413 and a data input/output bus 414 to the switching circuit 440. Further, when the control information relates to a data transfer operation, the control information is transferred via a control bus 415 and a data input/output bus 416 to the WSM 460.
It should be noted that a write operation to the memory 450 requires the WSM 460 when complicated control is necessary like writing to the EEPROM. In this case, the switching circuit 410 gives a rewrite instruction to the WSM 460 via the control bus 415 and the data bus 416 like a data transfer operation.
Next, a specific operation of the semiconductor memory device 490 will be described.
When data is externally read from the memory 430, the switching circuit 410 is instructed via the control bus 401 to read data from the memory 430. When control information received via the control bus 401 indicates a read operation from the memory 430, the switching circuit 410 gives a read instruction to the switching circuit 420 via the control bus 411, and the switching circuit 420 gives a read instruction to the memory 430 via a control bus 421.
When the memory 430 is instructed via the control bus 421 to perform a read operation, the memory 430 reads data stored in designated memory elements, and outputs the data via a data bus 422 to the switching circuit 420. The switching circuit 420 receives the data from the data bus 422, and transfers the data via the data bus 412 to the switching circuit 410.
The switching circuit 410 outputs the data received from the data bus 412 to outside of the memory device 490 via the data bus 402. A series of the above-described operations allows external read out from the memory 430.
Next, the case when data is externally written to the memory 430 will be described. A write instruction is transferred via the control bus 401 to the switching circuit 410 to the memory 430. Data to be written is input via the data bus 402 to the switching circuit 410.
When control information received via the control bus 401 is a write operation to the memory 430, the switching circuit 410 gives a write instruction via the control bus 411 to the switching circuit 420, and data to be written is input via the data bus 412 to the switching circuit 420.
The switching circuit 420 gives a write instruction via the control bus 421 to the memory 430, and inputs data to be written to the memory 430 via the data bus 422.
When the memory 430 is instructed via the control bus 421 to perform a write operation, data input via the data bus 422 is written to designated memory elements. A series of the above-described operations can achieve an external write operation to the memory 430.
It should be noted that an operation in which data is externally read from the memory 450 is similar to that in which data is externally read from the memory 430, and therefore a description thereof is herein omitted.
Next, the case when data is externally written to the memory 450 will be described. If memory elements constituting the memory 450 allow a simple write operation, such a write operation can be achieved by a control operation similar to the write operation to the memory 430. However, for example, if a memory which requires complicated control, such as an EEPROM, is used, the WSM 460 is required for controlling write operations.
In this case, a write control instruction is externally given via the control bus 401 to the memory 450. When data to be written is specified by the data bus 402, the switching circuit 410 instructs the WSM 460 to perform a write control operation via the control bus 415 and the data bus 416.
The write control instruction is transferred via a control bus 463 to the switching circuit 440, and data to be written is input to the memory 450 from the switching circuit 410 directly via a data bus 414, or data to be written is input via the data bus 416, then WSM 460, and then a data bus 464.
The switching circuit 440 uses a control bus 441 to control a write operation to the memory 450 so that data to be written is input via a data bus 442 to the memory 450.
When the WSM 460 is used, even if the memory 450 is a memory requiring complicated control operations, such as an EEPROM, a series of the above-described operations allow a write operation to the memory 450.
Next, a data transfer operation from the memory 430 to the memory 450 will be described. A data transfer operation is required mainly when data is transferred from a high write-speed memory to a low write-speed memory. This case will be described. It should be noted that a data transfer function from a low write-speed memory to a high write-speed memory is useful so as to reduce the load of an external control device, and can be implemented by a conventional technique. A control method therefor is similar to that when data is transfer from a high write-speed memory to a low write-speed memory, and therefore a description thereof is herein omitted.
When a data transfer operation instruction (control instruction by a control command) is externally given to the switching circuit 410 via the control bus 401 and the data bus 402, the switching circuit 410 transfers information required for data transfer, such as the receipt of the data transfer operation instruction, a region to which data is to be transferred, and the like, to the WSM 460 via the control bus 415 and the data bus 416.
When the WSM 460 is instructed via the control bus 415 and the data bus 416 to perform a data transfer operation from the memory 430 to the memory 450, the WSM 460 instructs the switching circuit 420 via a control bus 461 to read data to be transferred to the memory 430.
The switching circuit 420 reads data from the memory 430 designated by the control bus 461, via the control bus 421 and the data bus 422, and transfer the read data via a data bus 462 to the WSM 460.
The WSM 460, which received the data to be transferred from the switching circuit 420, uses the control bus 463 to instruct the switching circuit 440 to write the data to the memory 450.
The data to be written is transferred via the data bus 464 to the switching circuit 440. The switching circuit 440 uses the control bus 441 and the data bus 442 to carry out a write operation to the memory 450, which is the instruction given via the control bus 463 and the data bus 464.
When a plurality of pieces of data are transferred, the WSM 460 carries out the above-described data transfer operation for all of the designated data, thereby completing the data transfer operation.
Here, if a read operation from the memory 430 designated by the WSM 460 conflicts with an external control command issued to the memory 430, the switching circuit 420 judges the confliction of the control command information, and informs the WSM 460 of the confliction of the control command information using a judgment signal 425.
If the semiconductor memory device 490 is designed to permit access to the memory 430 during a data transfer operation, it is possible that external control information to the memory 430 conflicts with control information from the WSM 460. If such a confliction occurs, the operation of the switching circuit 420 varies depending on the specification of the semiconductor memory device 490. When an external memory operation is designed to have priority over a data transfer operation, the switching circuit 420 uses the control bus 421 and the data bus 422 to control the memory 430 to transfer read data, if in a read operation for example, via the data bus 412 to the switching circuit 410.
Conversely, if it is assumed that a data transfer operation has priority over an external control command, when a confliction occurs as to control information, the switching circuit 420 uses the control bus 421 and the data bus 422 to carry out a data transfer operation (an access operation to the designated memory 430) and informs the WSM 460 of the cancellation of an external memory operation using the judgment signal 425. In this situation, since it is possible that external access is not normally carried out, a means for externally checking whether or not a control is normally completed is required. In this case, the check operation instruction is externally given via the control bus 415 and the data bus 416 to the WSM 460. The WSM 460 uses the control bus 415 and the data bus 416 to transfer a content indicating the result of the judgment signal 425 to the switching circuit 410, and the content is output outside of the memory device 490 from the switching circuit 410 via the data bus 402.
Alternatively, another means for externally checking the completion of a memory operation may be achieved as follows. The judgment signal 425 is not transferred to the WSM 460, but instead the judgment signal 425 is transferred to the switching circuit 410, and only the switching circuit 410 is used to externally check the completion of a memory operation.
A control command to the memory 450 can be designed so that an external memory operation and a data transfer operation from the WSM 460 are separately carried out. Since such an operation is similar to that of the control of the memory 430, a description thereof is omitted.
As described above, in conventional techniques, a data transfer operation and an external memory operation can be separately carried out. However, when a data transfer operation has priority over an external memory operation, the external memory operation becomes more complicated than a typical memory. When an external memory operation has priority over a data transfer operation, the data transfer operation is affected, and a time required for the data transfer operation is elongated. Particularly, when an external memory operation is complicated, or when an external memory operation takes a long time, the probability that the external memory operation conflicts with the data transfer operation is dramatically increased. In these situations, the data transfer operation is affected to a large degree.
In a conventional semiconductor memory device having a function of transferring data between a high write-speed memory and a low write-speed memory, the high write-speed memory can be used for a working memory for a system, and the like. Further, if during a data transfer operation, next data to be transferred to the low write-speed memory is temporarily stored in another region in the high write-speed memory, the performance of the data transfer can be expected to be improved.
In an SRAM and a DRAM which are representative high write-speed memories, reading and writing are carried out at high speed in substantially the same cycles. The reading and writing can be controlled irrespective of the status of the device except for special situations. Further, in this case, verification of the reading or writing is not carried out. If there is a possibility that reading or writing fails due to a constraint on the state of the device, it is necessary that the success or failure of the control is output outside, and an external control device receives and displays the success-or-failure signal, for example.
To avoid such a complicated operation, the high write-speed memory often has priority over the external memory operation irrespective of whether or not a data transfer operation is being carried out.
However, interruption of a data transfer operation during an external memory operation may cause a reduction in data transfer rate. Particularly, when an external memory operation is frequent or a single control operation (memory operation) takes a long time, a reduction in data transfer rate is significant.
To avoid this, a dual port memory can be used as a memory at a data transferring end. Unfortunately, the dual port memory inevitably leads to an increase in cell area, and the like, and further leads directly to an increase in cost or an area occupied by elements, and the like.
The object of the present invention is to solve the above-described problems.
According to one aspect of the present invention, a semiconductor memory device comprises first and second memory sections including a plurality of memory elements, and a memory control section for allowing a data transfer operation between the first and second memory sections based on an external control command while allowing a memory operation to at least one of the first and second memory sections. At least one of the first and second memory sections include a plurality of small memory regions. The memory control section allows each of the plurality of small memory regions to be separately and simultaneously subjected to an access operation. Thereby, the above-described object is achieved. Access operations as used herein include memory operations, such as read operations, write operations, erase operations, verify operations, and the like, and further read and write operations to a memory in data transfer.
In one embodiment of this invention, the memory control section controls the plurality of small memory regions so that one small memory region is used for a data transfer operation while another small memory region is used for a memory operation and/or one small memory region is used for a memory operation while another small memory region is also separately used for another memory operation, thereby simultaneously executing the data transfer operation and the memory operation and/or the memory operations.
In one embodiment of this invention, the first and second memory sections include different memory elements, and one of the first and second memory sections having a higher-write speed includes a plurality of small memory regions.
In one embodiment of this invention, the memory control section has an access operation section for limiting an access period for at least one of the first and second memory sections to a minimum of that required for each access operation, and a third memory section for storing predetermined memory data within the access period limited by the access operation section.
According to another aspect of the present invention, a semiconductor memory device comprises first and second memory sections including a plurality of memory elements, and a memory control section for allowing a data transfer operation between the first and second memory sections based on an external control command while allowing a memory operation to at least one of the first and second memory sections. The memory control section has an access operation section for limiting an access period for at least one of the first and second memory sections to a minimum of that required for each access operation. Thereby, the above-described object is achieved.
In one embodiment of this invention, the semiconductor memory device further comprises an access completion signal generation section for generating an access completion signal when an access is completed. The access operation receives the access completion signal and ends the access period started by an access permission signal. Thereby, the above-described object is achieved.
In one embodiment of this invention, the memory control section has a third memory section for storing predetermined memory data within the access period limited by the access operation section, and the memory control section executes a data read operation within the access period limited by the access operation section when data is read from at least one of the first and second memory sections, and stores the read data to the third memory section. Therefore, for example, data read by a read operation requested to the higher-write-speed memory is latched, thereby making it possible to efficiently perform an operation of the higher-write-speed memory.
In one embodiment of this invention, the memory elements included in the first and second memory sections are of different types, and the memory control section reads data from one of the first and second memory sections having a higher-write speed.
In one embodiment of this invention, the memory control section writes data to at least one of the first and second memory sections within the access period limited by the access operation.
In one embodiment of this invention, the semiconductor memory device is integrated into a single semiconductor chip.
According to another aspect of the present invention, an information apparatus is provided in which the above-described semiconductor memory device is used to execute at least one of a data transfer operation and a memory operation, or at least two memory operations within an access period.
According to another aspect of the present invention, a method is provided for determining an access period for a semiconductor memory device. When an access is completed, an access completion signal is generated, and when the access completion signal is received, the access period started by an access permission signal is ended.
Functions of the present invention will be described below. One of the first and second memory sections which has a greater write speed is composed of a plurality of small memory regions in which a memory operation and a data transfer operation are separately carried out. The present invention provides a memory control section which enables simultaneous memory operations to the regions where one region is used for a data transfer operation while another region is separately subjected to an external access operation. Therefore, it is possible to simultaneously carry out a memory operation by an external control command and a data transfer operation by another control command in parallel. Further, memory operations by respective separate control commands can be simultaneously carried out in parallel.
Further, the memory control section limits an access period to a period for which a memory array is actually activated. Therefore, a memory operation and a data transfer operation, or separate memory operations can be efficiently carried out for an access period which is limited to the minimum of that required for each access operation. Therefore, for example, data read from a high write-speed memory in response to a read operation is latched so that the high write-speed memory can be efficiently operated.
Further, if a section comprising a plurality of regions in which a high-write-speed region can be separately operated, and a section for limiting a period, for which a memory array in the high-write-speed memory section is activated, to the minimum of that required are simultaneously used, access operations can be more efficiently carried out.
In any of the above-described cases, the probability that an external memory operation and a data transfer operation conflict can be reduced. Therefore, it is possible that a reduction in speed of a data transfer operation can be inhibited while priority is given to an external memory operation, or the probability that an external memory operation is interrupted can be reduced while priority is given to a data transfer operation.
Thus, the invention described herein makes possible the advantages of providing a semiconductor memory device capable of reducing a probability of confliction between an external memory operation and a data transfer operation, and an information apparatus using the semiconductor memory device, and a method for determining an access period for the semiconductor memory device.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.